The present invention generally relates to a programable logic array and a data processing unit using the same, such as a central processing unit.
Conventionally, when a desired logic is implemented using a programmable logic array (hereafter simply referred to as a PLA), a multi-stage logic circuit is used to mimimize the number of product terms. Normally, a multi-stage logic circuit is a two-stage logic circuit consisting of an AND circuit and an OR circuit. An output signal of the OR circuit is fed back to the input side of the AND circuit. Alternatively, the multi-stage logic circuit can be a plurality of PLAs connected in serial and parallel forms. Particularly, in a case where an instruction or command is decoded by a central processing unit (hereafter simply referred to as a CPU), it is advantageous to use the above-mentioned multi-stage logic circuit which processes a complex instruction system or to use a single PLA having a large number of product terms.
However, when such a PLA having a large number of product terms is used, it is necessary to reduce the number of product terms. For this purpose, a logic convolution process is needed. A logic convolution process is directed to grouping input lines of the PLA into two product term lines interchanging with each other so that unnecessary input lines are removed. With the logic convolution process, it becomes possible to minimize the structure of the PLA.
As described above, the logic convolution process reduces the size of the PLA. However, when configuring a CPU having a PLA using the above-mentioned logic convolution process, it is also necessary to provide instruction registers which store instructions for executing the logic convolution process and provide a timing control circuit which generates timing signals used for sending the instructions stored in the instruction registers to the PLA. In this case, it is necessary to provide interconnection lines between the provided instruction registers and the timing control circuits. As a result, the entire CPU size increases although the PLA itself is minimized. Further, programming of the logic convolution process is very troublesome, and thus there is a need for a large amount of work. Moreover, it is very difficult to modify the programmed PLA logic, since the logic convolution process is very complex. Furthermore, the signals supplied to the AND circuit (plane) from the instruction registers and the timing control circuits have large loads, and there is a possibility that the decoding speeds of the instructions are different from each other. In addition, a large amount of delay time occurs until the decoded signals are obtained, particularly when the multi-stage logic circuit is employed.